The present disclosure relates to an opto-electronic device package with a semiconductor sub-mount having surface mounting device (SMD) metal contacts.
Optoelectronic devices, such as light emitting diodes (LEDs), have various applications in consumer electronics. High-brightness LEDs, for example, can be used as light sources in space-limited applications where thermal management is important. The LEDs are optimized for display backlighting and illumination in automotive and transport, consumer, and general applications. Typical end-products include mobile telephone displays, flashes for cameras, retail and window displays, emergency lighting and signs, household appliances, and automotive instrument panels and exterior lighting, such as brake lights and turn signals.
Some high brightness LED packages are ceramic-based or employ plastic leadless chip carriers (PLCCs). Silicon-based packages, however, can facilitate manufacturing of the packages by leveraging mature silicon processing techniques. In one example, a LED chip is mounted within a recess of a silicon sub-mount. Feedthrough metallization extends through vias from the front-side recess to SMD contacts on the backside of the sub-mount and provides electrical connections for the LED's anode and cathode terminals. The SMD contacts allow the package to be mounted, for example, on a printed circuit board (PCB).
Formation of the backside contacts for the foregoing non-planar sub-mount typically requires a solder dam to restrain solder from enclosing the via cavities and thus forming larger voids inside the cavity area when the LED package is mounted on the PCB. The effect is aggravated by the fact that the solder provided by the PCB typically contains a large amount (e.g., 10-15 wt %) of flux that needs to outgas during soldering operations.
For non-planar backside contacts, a considerable amount of gas is likely to be entrapped during this process because the via structure comprises a relatively large enclosed volume. The voids formed can lead to difficulties in process repeatability because the amount of voiding varies statistically. The voids also can pose a considerable threat during thermal cycling. The gas-filled voids can expand during heating and potentially cause stress of the metallization system (e.g., solder and solderable metallization), which can lead, in some cases, to component failure (e.g., increased electrical resistance) as the result of partial or full delamination.
Another problem addressed by the present disclosure is that depositing a solder dam typically requires a physical vapor deposition (PVD) process for the metallization of the SMD-side of the sub-mount. It has been observed that the metal layers are considerably thinner inside the vias compared to the flat surface of the SMD side. In some cases, the metal thicknesses are up to 50% thinner. Thus, thicker metal deposition is required to circumvent full consumption of the metal layers during soldering inside the vias. However, PVD processes produce metal layers with a considerable amount of stress, so that a thicker layers of metal (e.g., by a factor of 2) may be difficult to achieve.
In addition, some designs (e.g., those that include a solder dam formed by a metal that is contained in a thin film metal stack) may require an additional mask for structuring a metal stack that includes a solder dam. Likewise, designs that use a photo-structurable polymer such as benzocyclo-butene (BCB) typically require additional masks for the BCB layers and for structuring the SMD pads or under bump metallization (UBM) (i.e., the metal stack that is deposited under the bump as part of the solder bumping process and typically has the combined features of adhesion layer, diffusion barrier, wetting layer and oxidation protection layer).